A key component of modern high-speed digital systems, having many interconnected digital chips, is the transceiver which includes a driver and a receiver. With increased circuit density and speed, the performance of the driver is crucial to the success of the system. To provide good performance several criteria must be met. These include providing adequate timing margin, maintaining good signal integrity, introducing low electromagnetic interference (EMI) emissions, providing low noise with low cross-talk, and consuming low power. Preferably, the driver is single-end rather than differential thereby providing reduced pin count and potential for reduced power dissipation.
Existing digital driver designs meet some but not all of the above-identified criteria. Typical CMOS drivers have a voltage swing from rail-to-rail. Consequently CMOS drivers tend to be noisy and exhibit very high power dissipation with capacitive loads which are even a moderate level. Typical TTL drivers have a smaller voltage swing than CMOS drivers, however the swing is uncontrolled and consequently power dissipation varies considerably. For both CMOS and TTL drivers, even with slew-rate control, EMI emissions are relatively high and timing margins are inadequate for many applications. Many of the criteria are met by typical ECL drivers. ECL drivers are analog in nature and have controlled output voltage swing and output impedance. With slew-rate control, ECL drivers offer good timing margins, good signal integrity, and introduce little noise. ECL drivers have differential outputs which introduce low EMI emissions and allow for low cross-talk. ECL drivers use a Class A output stage, consequently power dissipation is relatively high.